Exposure control device for a camera

ABSTRACT

An exposure control device is disclosed which has an extremely high accuracy as compared with the prior art, the error range being within a one-eighth step. For such a highly accurate control of exposure time, a value of exposure time to be determined is converted to a binary code of n bits, of which the lowest one bit is weighed one-eighth step. Based on the decimal number corresponding to the upper m bits of the binary code, the frequency of the control signal is adjusted and is used in reading out the lower (n - m) bits of the same binary code, whereby the period of actuation of the shutter is determined.

BACKGROUND OF THE INVENTION

1. Field of the Invention:

This invention relates to time interval control device, and more particularly to a time interval control device suitable for use in exposure control of a photographic camera and which operates with a very high accuracy such that the exposure time error is within a one-eighth step.

2. Description of the Prior Art:

There is known an exposure control device of the type for controlling the shutter speed of a camera in accordance with the level of brightness of an object being photographed, wherein information representative of the object brightness level is converted by an analog-to-digital converter to a digital code which, after once being memorized, is digitally read out by a digital circuit to control the period of actuation of the shutter, as, for example, disclosed in U.S. Pat. No. 3,824,608.

The conventional type exposure control device, however, controls exposure time in one-step progression, the exposure time error amounting to as large as ± 1/2 step, and accordingly has a drawback that the period of actuation of the shutter can not be controlled with high accuracy. The term "one step" herein used refers to a particular unit of exposure time expressed by APEX value. (APEX: Additive System of Photographic Exposure). The relationship between APEX values and corresponding time intervals in seconds is shown in FIG. 1. For example, APEX value "0" corresponds to one second, APEX value "1" to 1/2 second, and APEX value "1/8" to 0.917 second.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a time interval control device capable of converting a digitally coded time information to an actual time interval with high accuracy.

Another object of the invention is to provide an exposure control device capable of controlling exposure time with extremely high accuracy.

Another object of the invention is to provide an exposure control device in which the error range of exposure time is within 1/8 step.

Another object of the invention is to provide an exposure control device employing a very simple circuit structure while nevertheless preserving extremely high exposure control accuracy.

Another object of the invention is to provide an exposure control device which operates in 1/8 step exposure time progression and which employs a circuit for reading out a value of exposure time memorized in 1/8 step unit.

Another object of the invention is to provide an exposure control device in which the circuit for reading out a value of exposure time memorized in 1/8 step unit is of very simple structure.

Another object of the invention is to provide an exposure control device having a frequency divider capable of dividing the frequency of a reference pulse train by 2 k, (wherein k is an integer) and wherein the frequency divider serves as the circuit for reading out a value of exposure time memorized in 1/8 step unit.

Other objects of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a table of numerical values for various exposure control parameters each expressed in the conventional unit and the APEX unit.

FIG. 2 is a table of numerical values for exposure time in second, APEX, and binary and octinary codes.

FIG. 3 is a table of numerical values showing the size of errors which result when 2^(z/8) is approximated by [1 + z/8].

FIG. 4 is a block diagram of an exposure time control according to one embodiment of the present invention.

FIG. 5 is a schematic electrical circuit diagram of the system of FIG. 4.

FIG. 6 is a pulse timing chart showing the manner in which the frequency divider of FIG. 5 may be used.

FIG. 7 is a pulse timing chart showing the manner in which the circuit of FIG. 5 may be used.

FIG. 8 is a schematic electrical circuit diagram of a time period control system according to another embodiment of the present invention.

FIG. 9 is an example of a subtraction circuit usable in any one of the blocks S₁ through S₁₁ of FIG. 8.

FIG. 10 is a fragmentary schematic electrical circuit diagram of still another embodiment of the present invention.

FIG. 11 is a perspective view of a shutter speed setting means adapted for association with the encoding section of the circuit of FIG. 10.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The mathematical principle on which the present invention is based will first be explained with reference to FIGS. 1, 2 and 3. In deriving an exposure value from preselected numerical values in the conventional units of various exposure control parameters such as shutter time in seconds, diaphragm aperture in F-value, film sensitivity in ASA, and object luminance in foot-lambert, it is required to represent these parameters in a common unit. For such a unit, the present invention employs a particular APEX unit. An example of representation of numerical values of the exposure control parameters in APEX unit in connection with those in the conventional units is shown in FIG. 1. In the case of exposure time, for example, while the numerical values T in seconds is in geometric sequence with a factor of 1/2, the numerical values Tv in APEX unit is in arithmetic sequence. In order to control the exposure time in progression of one-eight APEX unit steps, FIG. 2 provides a set of binary codes in six bits along with the corresponding set of octinary codes. It is to be noted in FIG. 2 that one-eight of the APEX unit corresponds to a factor of 1/1.09 for sequence of exposure time values in second, because of 8√2 = 1.09. Each of the binary codes has lower three bits, designated by reference characters 1/2, 1/4 and 1/8, determining the decimal fraction of an APEX value, and has higher three bits, designated by reference characters 4, 2 and 1, determining an one of the integers from "0" to "7" inclusive of the same APEX value.

Now assuming that the reference time interval is 1/256 second which corresponds to an APEX value of 8, and that an exposure control system is responsive to the object luminance level to derive an exposure value, in this instance, an exposure time Tv in APEX unit, the exposure time differs from the reference time interval by a number of steps equal to 8-Tv. Expressing the APEX value 8-TV in the octinary system, as m + (n/8, wherein m and n are integers from 0 to 7 inclusive, we have a formula of deriving an actual exposure time interval in second from this APEX value, as defined by 1/250 + 2.sup..sup.[ m⁺ (n/8)^(]) . The digital computation of a factor 2^(n/8) is of very complicated process. Therefore, according to the present invention, the factor 2 ^(n/8) is approximated by a factor 1 + (n/8). The numerical values of deviation from the true values under this approximation are given in FIG. 3. It is evident from FIG. 3 that the error estimated by the APEX unit-step is 0.085 step at maximum when n = 4, and consequently this error is negligible as compared with the one-eighth unit-step accuracy of exposure time control. In conclusion, the exposure time derived in APEX unit from the exposure control sytem can be reduced to an actual time interval T in second by computation based on the following formula:

    T = (1/256) × 2.sup.m × [ 1 + n/8]= (1/2048) × 2.sup.m × (8 + n)

Referring now to FIG. 4, there is shown one embodiment of a time interval control system having a function of performing the above-defined computation according to the present invention as associated with an automatic exposure control system for a photographic camera. The automatic exposure control system may be of the conventional type, and is illustrated as having exposure control parameter setting circuit means EF capable, upon setting of preselected values of diaphragm aperture and film speed in the conventional units of producing respective electrical signals proportional to the selected values of these parameters in the APEX units, and light measuring circuit means LM responsive to the level of luminance of an object being photographed for producing an electrical signal proportional to the object luminance level in the APEX unit. In the illustrated embodiment, the time interval control system includes an analog-to-digital converter 1 receptive of both of the ouputs from the means EF and LM of the exposure control system for converting a combined output thereof to a corresponding six-bit binary coded information as a function of (8 - Tv), a store register 2 having six bits, designated by suffixed reference numerals 2₁, 2₂ , 2₃, 2₄, 2₅ and 2₆, connected to respective output stages of the A-D converter 1 for storing the binary coded information in the form of 2^(m) × (n/8), the number `m` being stored in the first three bits 2₆, 2₅, and 2₄, and the number `n` being stored in the second three bits 2₃, 2₂ and 2₁, a 1-2-4 binary coded integral control register 4 having three bits, designated by suffixed numerals 4₃, 4₂ and 4₁, connected to respective outputs AR₆, AR₅ and AR₄ of the first three bits 2₆, 2₅ and 2₄ respectively, and a 1-2-4-8 binary coded fractional control register 6 having four bits, three of which, designated by suffixed numerals 6₁, 6₂ and 6₃, are connected to respective outputs AR₁, AR₂ and AR₃ of the register 2 respectively, and the other of which, designated by a suffixed numeral 6₄ is connected to starting means not shown. The bit 6₄ is weighted 8, and is set to a binary 1 condition when the starting means is actuated. As a result, at the time of actuation of the starting means, the binary coded fractional control register 6 provides information respresentative of the number 8 +n).

In accordance with the present invention, a binary frequency divider 10 is provided to multiply the pulse frequency, fst, in this instance, fst = 2048 in sec., of a clock pulse train Tst applied thereto through an AND gate A₃ by a set of decimal fractions, namely, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 and 1/128, so as to produce eight pulse trains of different frequency as shown in the pulse timing chart of FIG. 6, wherein a first pulse train with fst = 2048 in sec. appears at a first output terminal T₁ of the frequency divider 10, a second pulse train with 1/2.sup.. fst at the second output terminal thereof, a third pulse train with 1/4.sup.. fst at the third output terminal T₃, a fourth train with 1/8.sup.. fst at the fourth output terminal T₄, a fifth pulse train with 1/16.sup.. fst at the fifth output terminal T₅, a sixth pulse train with 1/32.sup.. fst at the sixth output terminal T₆, a seventh pulse train with 1/64.sup.. fst at the seventh output terminal T₇, and an eighth pulse train with 1/128.sup.. fst at the eighth output terminal T₈. All of these eight pulse trains T₁ through T₈ are applied to a pulse frequency selector 12 which is controlled by the output of the 1-2-4 binary coded integral control register 4, so as to select which of the pulse trains T₁ through T₈ is to be passed to a subtractor 14, thereby determining the period of time during which a count-down operation of the subtractor 14 occurs in synchronism with one pulse in the passed or selected pulse train to subtract one from the number (8 + n) previously registered in the 1-2-4-8 binary coded fractional control register 6. At the time the number (8 + n) has been counted down completely, or all of the four bits in the register 6 are reset to their binary 0 conditions, a zero detector 8 produces an output signal of low level (hereinafter referred to as binary "0" level). So long as any one of the four bits of the register 6 remains in the binary "1" condition, the zero detector 8 produces an output signal of high level (hereinafter referred to as binary "1" level). The output of the zero detector 8 is applied to the gating control input of the AND gate A₃, and is also connected to a shutter control circuit not shown of the exposure control system.

Referring to FIG. 5, there is shown an example of an electrical circuitry usable in the time interval control system of FIG. 4. In FIG. 5, the binary coded integral control register 4 comprises three flip-flops F₄, F₅ and F₆ connected at their set-direct terminals SD to respective output terminals AR₄, AR₅ and AR₆ of the store register 2 respectively, upon application of signals to the set-direct terminals SD from the output terminals AR₂, AR₅ and AR₆ to be set either to the binary "1" condition, or the binary "0" condition. The binary coded fractional control register 6 comprises four flip-flops F₁, F₂, F₃ and FD connected at their set-direct terminals SD to respective output terminals AR₁, AR₂ and AR₃ of the store register 2 and the start signal input terminal START respectively. At the time when the flip-flop FD is set to the binary "1" condition in response to the start signal applied to the set-direct terminal SD thereof, the flip-flops F₁, F₂ and F₃ are supplied with the respective outputs from the lower three bits 2₁, 2₂ and 2₃ of the store register 2. The zero detector 8 comprises an OR gate OR₁ connected to all of the first output terminal Q's of the four flip-flops F₁, F₂, F₃ and FD and having a single output connected to the gating control input of the AND gate A₃. The frequency divider 10 comprises seven T-type flip-flops FT₁ through FT₇, the first flip-flop FT₁ having an input terminal T connected to the output of the AND gate A₃, the second flip-flop FT₂ having an input terminal T connected to an output terminal of the first flip-flop FT₁, the third flip-flop FT₃ having an input terminal T connected to an output terminal Q of the second flip-flop FT₂, and so on.

The pulse frequency selector 12 comprises an arrangement of 32 gating elements a₀ through a₃₁ on seven conductors 1₀ through 1₇ and an OR gate OR₂ connected to all of the conductors 1₀ through 1₇. Gate element a₀ is gated on the pass the first pulse train T₁ of FIG. 6 to the OR gate OR₂ when all of the three flip-flops F₄, F₅ and F₆ are in their binary "0" conditions, under which an output is caused to appear in conductor 1₀ by gate elements a₈, a₉ and a₁₀ connected through respective inverters IN₆, IN₅ and IN₄ to the outputs Q₇, Q₆ and Q₅ of flip-flops F₆, F₅ and F₄ respectively. Gate element a₁ is gated on to pass the second pulse train T₂ when flip-flops F₆, F₅ and F₄ are in the binary "0," "0" and "1" conditions respectively, under which an output is caused to appear in conductor 1₁ by gate elements a₁₁, a₁₂ and a₁₃ connected to inverters IN₆ and IN₅ and output Q₅ respectively. Gate element a₂ is gated on to pass the third pulse train T₃ when flip-flops F₆, F₅ and F₄ are in the binary "0," 1 and "0" conditions respectively, under which an output is caused to appear in conductor 1₂ by gate elements a₁₄, a₁₅ and a₁₆ connected to inverter IN₆, output Q₆ and inverter IN₄ respectively. Gate element a₃ is gated on to pass the fourth pulse train T₄ when flip-flops F₆, F₅ and F₄ are in the binary "0," "1" and "1" conditions respectively, under which an output is caused to appear in conductor 1₃ by gate elements a₁₇, a₁₈ and a₁₉ connected to inverter IN₆ and outputs Q₆ and Q₅ respectively. Gate element a₄ is gated on to pass the fifth pulse train T₅ when flip-flops F₆, F₅ and F₄ are in the binary "1," "0" and "0" conditions respectively, under which an output is caused to appear in conductor 1₄ by gate elements a₂₀, a₂₁ and a₂₂ connected to output Q₇ and inverters IN₅ and IN₄ respectively. Gate element a₅ is gated on to pass the sixth pulse train T₆ when flip-flops F₆, F₅ and F₄ are in the binary "1," 0 and "1" conditions respectively, under which an output is caused to appear in conductor 1₅ by gate elements a₂₃, a₂₄ and a₂₅ connected to output Q₇, inverter IN₅ and output Q₅ respectively. Gate element a₆ is gated on to pass the seventh pulse train T₇ when flip-flops F.sub. 6, F₅ and F₄ are in the binary "1," "1" and "0" conditions respectively, under which an output is caused to appear in conductor 1₆ by gate elements a₂₆, a₂₇ and a₂₈ connected to outputs Q₇ and Q₆ and inverter IN₄ respectively. Gate element a₇ is gated on to pass the eighth pulse train T₈ when all of flip-flops F₄, F₅ and F₆ are in their binary "1" conditions, under which an output is caused to appear in conductor 1₇ by gate elements a₂₉, a₃₀ and a₃₁ connected to outputs Q₇, Q₆ and Q₅ respectively. It is evident that the pulse frequency selector 12 provides a pulse train of a pulse period corresponding to 2^(m) × Tst.

The subtractor 14 comprises three exclusive OR gates E₁, E₂ and E₃, and two AND gates A₁ and A₂ connected to each other and to the flip-flops F₁, F₂, F₃ and FD of the binary coded fractional control register 6 in such a manner as to be described below. Each of the four flip-flops F₁, F₂, F₃ and FD has a control pulse or first input terminal CP connected to the output terminal SB of the pulse frequency selector 12 so that when a pulse of the selected pulse train is applied to the input terminal CP, the flip-flop is inverted from one binary condition to the other, and first and second outputs terminals Q and Q at which an output appears when the flip-flop is in the binary "1" or "0" condition respectively. Flip-flop F₁ has the first output terminal Q connected to the OR gate OR₁ of the zero detector 8, and has the second output terminal Q connected to another input terminal D thereof so that, upon application of a pulse to the first input terminal CP, flip-flop F₁ is inverted. Flip-flop F₂ has the first output terminal Q connected to the OR gate OR₁, and has a seond input terminal D connected to the output terminal of the first exclusive OR gate E₁ having two inputs one of which is connected to the first output terminal Q of flip-flop F₂, and the other of which is connected to the second output terminal Q of flip-flop F₁, so that flip-flop F₂ is inverted by application of a pulse to the first input CP thereof, only when flip-flop F₁ is in the binary "0" condition. Flip-flop F₃ has the first output terminal Q connected to the OR gate OR₁, and has the second input terminal D connected to the output terminal of the second exclusive OR gate E₂ having two input terminals, one of whcih is connected to the first output terminal Q of flip-flop F₃, and the other of which is connected through the first AND gate A₁ to the second output terminal Q of flip-flops F₁ and F₂, so that flip-flop F₃ is inverted by application of a pulse to the first input terminal CP thereof only when flip-flops F₁ and F₂ are simultaneously in the binary "0" conditions. Flip-flop FD has the first output terminal Q connected to the OR gate OR₁, and has the second input terminal D connected to the output of the third exclusive OR gate E₃ having two inputs, one of which is connected to the first output terminal Q of flip-flop FD, and the other of which is connected through AND gates A₁ and A₂ to the second output terminals Q of flip-flops F₁, F₂ and F₃, so that flip-flop FD is inverted by application of a pulse to the first input terminal CP thereof only when flip-flops F₁, F₂ and F₃ are simultaneously in the binary "0" conditions.

The operation of the electrical circuit of the time interval control system of FIGS. 4 and 5 will next be described in connection with FIGS. 6 and 7.

Now assuming that an APEX value of exposure time derived from the exposure control factor setting circuit means EF and the light measuring circuit means LM is 5.3 in the octanary system which corresponds to 5.375 in the denary system to 101011 in the binary system, and to 1/39.0 second as is understandable from FIG. 2, the A-D converter 1 converts this exposure time in the APEX unit to a binary code based on the formula (8 -Tv) = 8.0 - 5.3 = 2.5. It is to be noted with respect to the formula 2^(m) × (8 + n) that m = 2 and n = 5. The binary code corresponding to the octanary number 2.5 is 010101 which is previously registered in the store register 2.

When a shutter release button not shown of the camera is depressed, a starting pulse of wave form shown in FIG. 7 is applied to the set-direct terminal SD of flip-flop FD in synchronism at the leading edge of the starting pulse with the tailing edge of a pulse of clock pulse train Tst, thereby flip-flop FD is set to the binary "1" condition. In synchronism with the setting of flip-flop FD, there is caused by not shown means known in the art the flip-flops F₆, F₅ and F₄ in the binary integral control register 4 and the flip-flops F₃, F₂ and F₁ in the binary fractional control register 6 all to be set to their respective binary conditions in accordance wt with the outputs of the store register 2, namely, to the binary "0," "1," "0," "1," "0" and "1" conditions respectively. Responsive to the binary 0 output appearing in the output lead Q₇ of flip-flop F₆, inverter IN₆ actuates gate elements a₈, a₁₁, a₁₄ and a₁₇. As the binary "1" output appears in the output terminal Q₆ of flip-flop F₅, gate elements a₁₅, a₁₈, a₂₇ and a₃₀ are actuated directly by the binary "1" output. Responsive to the binary "0" output appearing in the output terminal Q₅, the inverter IN₄ actuates gate elements a₁₀, a₁₆, a₂₂ and a₂₈. As a result, an output appears in the common conductor 1₂ of gate elements a₁₄, a₁₅ and a₁₆, so that gate element a₂ is gated on to pass the third pulse train T₃ with a frequency of 2048 × (1/2)² as the parameter "m" is 2.

As shown in FIG. 7, flip-flops F₁, F₂, F₃ and FD in the binary coded fractional control register 6 produce outputs appearing at output terminals Q₁, Q₂, Q₃ and Q₄ respectively in synchronism with occurrence of the starting pulse, causing the zero detector 8 to produce an output which in turn causes the camera shutter to be opened through a shutter control circuit 50, and which also causes the third AND gate A₃ to be gated on to pass the clock pulse train Tst to the frequency divider 10. As the gate element a₂ is gated on by the binary coded integral control register 4 to select the third pulse train T₃, the first input pulse of pulse train T₃ is applied to the control pulse input terminal of each of flip-flops F₁, F₂, F₃ and FD, thereupon only the first flip-flop F₁ is inverted into the binary "0" condition causing the binary "0" output to appear at the output terminal Q₁ of flip-flop F₁. Upon advent of the second input pulse T₃ on register 6, flip-flops F₁ and F₂ are inverted from their binary "0" to "1" conditions, and flip-flop F₃ is inverted from its binary "1" to "1" condition, as flip-flops F₁ and F₂ are in the binary "0" conditions before the advent of the second input pulse T₃, while flip-flop FD remains uninverted. Upon advent of the third input pulse T₃ on the register 6, only the first flip-flop F₁ is inverted from the binary "1" to "0" condition, and the other flip-flops F₂, F₃ and FD remain uninverted. Such a count-down operation repeats itself each time an input pulse is applied to the register 6 until the thirteenth input pulse of pulse train T₃ is applied to the register 6, as can be seen from FIG. 7. Upon setting of the first flip-flop F₁ to the binary "0" condition by application of the thirteenth input pulse thereto, the zero detector 8 produces no output, thereby the camera shutter is closed, and the clock pulse train Tst is blocked by AND gate A₃ from entering the divider 10. The period of actuation of the camera shutter is consequently determined as 2^(m) × (8 + n) × Tst, wherein Tst is the time interval in second between the successive two clock pulses, namely, 4 × (1/2048) × (8 + 5 = 1/39.4 second. The error estimated as a difference between this value 1/39.4 and the true value 1/39.0 is about 1 per percent. Therefore, it is to be understood that the accuracy of exposure time control is as high as an order of less than one-eighth APEX unit step.

Referring to FIG. 8, there is shown another embodiment of a time interval control system according to the present invention as applied to an exposure control circuit for controlling the period of actuation of the electronic shutter of a camera. Whilst the first embodiment of the invention is adapted to count the number of pulses defined as (8 + n) with a modification of the clock pulse frequency, 2048 per second, as dividing by 2^(m), the second embodiment is to count the number of pulses defined as 2^(m) (8 + n) at the same clock pulse frequency regardless of variation of the parameter m, provided that the value of reference time interval, e.g., 1/256 second remains unchanged.

In accordance with the second embodiment of the invention, there are provided fourteen flip-flops F.F. 1 through F.F.14, with F.F.12, F.F.13 and F.F.14 constituting a binary coded integral control register and connected through respective signal transmission lines AR₄, AR₅ and AR₆ to the first three bits 2₄, 2₅ and 2₆ of a store register 2 respectively, with F.F.8, F.F.9 and F.F.10 constituting a binary coded fractional control register and connected through respective signal transmission lines AR₁, AR₂ and AR₃ at the set-direct terminals thereof with the second three bits 2₁, 2₂ and 2₃ of the store register 2 respectively, and with F.F.11 connected at the set-direct terminal thereof to a START signal generator not shown. With this arrangement of the flip-flops F.F.8 through F.F.14, it is possible to register a binary coded information representative of the numbers m and (8 + n) in a manner similar to that shown in the first embodiment of the invention.

Eleven subtractor elements S₁ through S₁₀ are provided for connection with flip-flops F.F.1 through F.F.11 in such a manner as to perform a count-down operational identical to that of the circuit of FIG. 5 each time a clock pulse is applied to the clock pulse input terminals CP of F.F.'s 1 through 11. As shown in FIG. 9, each of the substractor elements S₁ through S₁₁, for example, element S₆ comprises an exclusive OR gate Es having two input terminals IN and Cin the former input terminal IN of which is connected to an output Q of F.F.6 and the latter terminal Cin of which is connected to the output terminal of an OR gate 8, and having an output terminal OUT connected to an input terminal D of F.F. 6, and an AND gate As having two terminals, one of which is connected through an inverter INs to the output terminal Q of F.F. 6, and the other of which is connected to the terminal Cin, and having an output terminal Cout connected through an OR gate 9 to the C in terminal of subtractor element 7.

Eight AND gates A₅ through A₁₂ are provided in combination with three inverters IN₄, IN₅ and IN₆ for cooperation with the three flip-flops F.F.12, F.F.13 and F.F.14 in such a manner that an output of high level or binary "1" level appears at the output terminal of one of the AND gates A₁₂ through A₅ when m = 0, 1, 2, 3, 4, 5, 6 or 7 respectively. For this purpose, AND gate A₅ has three input terminals connected to respective output terminals Q of F.F.'s 12, 13 and 14. AND gate A₆ has three input terminals, one of which is connected through inverter IN₄ to the output terminal Q of F.F.12, and the other two of which are connected to the output terminals Q of F.F's 13 and 14. AND gate A₇ has three input terminals one of which is connected through inverter IN₅ to the output terminal Q of F.F. 13 and the other two of which are connected to the output terminals Q of F.F.'s 12 and 14. AND gate 8 has three input terminals, two of which are connected through inverters IN₄ and IN₅ to the output terminals Q of F.F.'s 12 and 13, and the other of which is connected to the output terminal Q of F.F. 14. AND gate A₉ has three input terminals, one of which is connected through inverter IN₆ to the output terminal Q of F.F. 14, and the other two of which are connected to the output terminals Q of F.F.'s 12 and 13. AND gate 10 has three input terminals, two of which are connected through inverters IN₄ and IN₆ to the output terminals Q of F.F.'s 12 and 14, and the other of which is connected to the output terminal of F.F. 13. AND gate 11 has three input terminals, two of which are connected through inverters IN₅ and IN₆ to the output terminals Q of F.F.'s 13 and 14, and the other of which is connected to the output terminal Q of F.F. 12. AND gate 12 has three input terminals, all of which are connected through inverters IN₄, IN₅ and IN₆ to the output terminals of F.F. 12, 13 and 14 respectively.

The output terminal of AND gate A₅ is connected to the input terminal Cin of subtractor element S₁. The output terminals of AND gates A₆ through A₁₂ are connected through OR gates OR₄ through OR₁₀ to subtractor element S₂ through S₈ respectively. The output terminal Cout of subtractor element S₁ is connected through OR gate OR₄ to the input terminal Cin of subtractor element S₂, and the output terminal Cout of subtractor element S₂ is connected through OR gate OR₅ to the input terminal Cin of subtractor S₃, and so on. The output terminal Cout of subtractor element S₈ is connected to the input terminal Cin of subtractor element S₉, the output terminal Cout of subtractor element S₉ is connected to the input terminal Cin of subtractor element S₁₀, and the output terminal Cout of subtractor element S₁₀ is connected to the input terminal Cin of subtractor element S₁₁. All of the output terminals of F.F.'s 1 through 11 are connected to an OR gate 3 having an output terminal connected to a shutter control circuit 50 and to one of two input terminals of an AND gate A₄, the other of which is supplied with a clock pulse train Tst. The output terminal of AND gate A₄ is connected to all of the clock pulse input terminals CP of F.F.'s 1 through 11.

In operation, an APEX value of exposure time Tv to be converted to an actual time interval is given as 5.3 in the octanary scale to the A-D converter 1 in which it is converted to a binary code 010101 based on the formula: Number of steps in APEX unit deviated from the reference time interval, it this instance, 1/256 second = 8.0 - Tv = 2.5 in the octanary scale. The binary code "010101" is registered in the respective bits of register 2. In synchronism with occurence of a pulse at the set-direct terminal of flip-flop F.F. 11, the binary coded information is applied from register 2 to F.F.'s 14, 13, 12, 10, 9 and 8 through transmission lines AR₆ through AR₁ respectively, thereby F.F.'s 14, 13 and 12 are set to the binary 0, 1 0 conditions respectively, and F.F.'s 11, 10, 9 and 8 are set to the binary "1," "1," "0," "1" conditions respectively in a manner similar to that shown in connection with FIGS. 5, 6 and 7. F.F.'s 12, 13 and 14 are decoded by AND gates A₅ through A₁₂, causing only one AND gate, namely, A₁₀ to produce an output of high level, while permitting the other AND gates to produce outputs of low level. The output of AND gate A₁₀ is applied through OR gate 8 to the input terminal Cin of subtractor element S₆, whereby F.F.'s 6 through 11 are rendered effective for counting-down operation, and F.F.'s 1 through 5 remain ineffective during this counting-down operation. In other words, the counting-down operation proceeds to count the number of clock pulses corresponding to the binary code "110100" initially registered in F.F.'s 11 through 6 respectively, and which is equal to the decimal number 2^(m) × (8 + n) = 4(8 + 5) = 52.

After AND gate 4 is gated on in synchronism with occurence of outputs of high level appearing at the output terminals Q₁, Q₃ and QD of F.F.'s 8, 10 and 11, the first input pulse of the clock pulse train passing through the thus gated AND gate 4 applied to the input terminal CP of each of F.F.'s 6 through 11, thereby F.F.'s 6, 7 and 8 are inverted and F.F.'s 9, 10 and 11 remain uninverted. This is because subtractor element S₆ passes the output of AND gate 10 to the input terminal D of F.F. 6 causing F.F. 6 to be inverted each time an input pulse is applied to the input terminal CP thereof, and because the output of the binary "0" level applied from F.F. 6 to the input terminal IN of subtractor element S₆ is inverted to a signal of the binary "1" level by the inverter INs thereof and then applied to the AND gate As thereof, causing the AND gate As to produce an output which is then applied to the input terminal Cin of the next subtractor element 7. Further, in a similar manner to the above, an output is applied from the output terminal Cout of subtractor element 7 to the input terminal Cin of the next subtractor element 8, but no output is applied from the output terminal Cout of subtractor element 8 to the input terminal Cin of the next subtractor element S₉ because F.F. 8 has the binary "1" condition preventing the AND gate As of subtractor element 8 from being gated by the output from subtractor element 7. Such a binary one-unit counting-down procedure repeats itself until the fifty-second clock pulse occurs. At the moment the tailing edge of the 50-second clock pulse passes the AND gate A₄, the duration of actuation of the OR gate OR₃ is terminated to close the AND gate A₄ and the camera shutter through the shutter control circuit 50. Thus, the period of actuation of the camera shutter is determined as 52 × 1 / 2048 = 1/39.4 second, provided that the pulse frequency of the clock pulse train is 2048 per second.

The present invention has been described in connection with two specific examples wherein an information in the form of an APEX value of exposure time as an exposure value derived from an automatic exposure control system is converted by the analog-to-digital converter 1 to a corresponding binary coded information in an automatic manner. Such examples can be changed in many ways, as for example, adapted to the purpose of manually setting the register 2 to a particular binary condition dependent upon a preselected exposure time. An example of a manually operating time interval control system is fragmentally shown in FIGS. 10 and 11.

FIG. 10 shows an encoder 100 adapted for operative association with a shutter speed selector shown in FIG. 11. The encoder 100 comprises a battery 101, a power switch 102, six switch element 103 through 108 connected between a common positive bus 118a connected through the power switch 102 to the positive terminal of the battery 101 and respective bits of the register 2 through first lead wires 103 through 108a and second lead wires 109 through 114a respectively, and six resistors 109 through 114 connected between a common negative bus and respective points on connections between the first lead wires 103a through 108a and the second lead wires 109a through 114a respectively. An example of construction and arrangement of the six switch elements 103 through 108 is shown in FIG. 11, wherein 116 is a shutter speed selector dial having cut thereon graduations representing a series of shutter speeds in second and cooperative with a stationary index 117 provided on a camera housing not shown. The shutter dial 116 is fixedly mounted on a shaft 115 at one end thereof, and the opposite end of which fixedly carries a code disk 118 made of a conducting material and having a peripheral side slidably engaging with one end of the lead wire 118a connected to the positive bus of the circuit of FIG. 10. The disk 118 is provided with six concentrical resistor tracks A through F cooperative with switch contacts 108 through 103 respectively as arranged upon rotation of the dial 116 to be slidable on the respective tracks A through F, each track being divided into 64 parts, though illustrated with far smaller parts for purpose of clarity, some parts of which are electrically conductive and the other parts of which are electrically insulated. The arrangement of these parts in all the tracks A through F is such that when a graduation representing a desired shutter speed, for example, 1/39 second is placed in alignment with the stationary index 117, switch elements 103, 105 and 107 are closed, and switch elements 104, 106 and 108 and left open to set the bits 6, 5, 4, 3, 2 and 1 of register 2 to the binary "0," "1," "0," "1" "0" and "1" conditions respectively. The subsequent operation will proceeds in a manner similar to that shown in connection with FIGS. 6 and 8.

It will be seen from the foregoing description that according to the present invention, the exposure time error can be limited to less than the one-eighth step. Further, the present invention contemplates the use of a frequency divider of simple structure such as comprising a plurality of cascade-connected flip-flops arranged in the time interval control circuit to divide the pulse frequency of a clock pulse train by a factor 1/2^(m), wherein m is an integer determined as equal to the decimal number of a binary code registered in the higher bits of the register 2, or otherwise would necessitate "rate multiplier" thereby the complexity of the circuit would be increased with increase in the production cost thereof.

The present invention has been described in detail with particular reference to preferred embodiments thereof, but it will be understood that variations and modificatios can be effected within the spirit and scope of the invention as described hereinabove and as defined in the appended claims. 

What is claimed is:
 1. An electric shutter control device comprising:a. photosensitive means for converting the intensity of light into a first electrical signal corresponding to the intensity; b. an analog-to-digital converter for converting said first electrical signal to a digital signal of n bits, wherein n is an integer; c. register means including an integral part register which stores an integral part of said digital signal of n bits and a fractional part register which stores a fractional part of the digital signal of n bits; d. a frequency divider for forming a plurality of first control signals having frequencies differentiated from each other by a multiplier 1/2k, wherein k is an integer; e. a selecting circuit responsive to the content of said integral part register for selecting one of said control signals from said frequency divider; f. a detecting circuit to said selecting circuit and said register means for detecting the content of the fractional part register and producing a second control signal when a predetermined relationship occurs between the number of pulses of the first control signal and the content of the fractional part register; and g. shutter control means responsive to the second control signal from said detecting circuit from controlling the period of actuation of the shutter.
 2. An electric shutter control device according to claim 1, wherein said register means includes a plurality of flip-flop circuits.
 3. An electric shutter control device according to claim 1, wherein said detecting circuit comprises:a. a subtracting circuit responsive to the first control signal for subtracting the content memorized in said fractional part register; and b. detecting means for producing a second control signal when the content of said fractional part register has reached a predetermined level as said content is subtracted by said subtracting circuit.
 4. An electric shutter control device according to claim 3, wherein said detecting means consists of an OR gate connected to said register means.
 5. An electric shutter control device comprising:a. a light measuring circuit for converting the intensity of light into a first electric signal corresponding to the logarithm of said intensity; b. an analog-to-digital converter for converting said first electrical signal to a digital code signal of n bits, wherein n is an integer; c. register means including an integral part register which stores an integral part of said digital signal of n bits and a fractional part register which stores a fractional part of the digital signal of n bits; d. a frequency divider for forming a plurality of first control signals having frequencies differentiated from each other by a multiplier 1/2k, wherein k is an integer; e. a selecting circuit responsive to the content in the integral part register for selecting one of said first control signals from said frequency divider; f. a substracting circuit for subtracting the content stored in the fractional part register in response to said first control signal selected by said selecting circuit; g. detecting means having input terminals respectively connected to output terminals of said fractional part register upon attainment of the content of said fractional part register to a predetermined level for producing a second control signal; and h. shutter control means responsive to said second control signal from said detecting circuit for closing the shutter.
 6. An electric shutter control device according to claim 5, wherein said frequency divider includes a plurality of cascade-connected flip-flip circuits.
 7. An electric shutter control device according to claim 6, further including gate means for applying a reference signal with a predetermined frequency to a first stage of said divider.
 8. An electric shutter control device comprising:a. a shutter speed selector; b. an encoder adapted for operative association with the shutter speed selector and generating a digital signal of n is an integer; c. register means consisting of an integral part register which stores an integral part of said digital signal of n bits and a fractional part register which stores a fractional part of the digital signal of n bits; d. a frequency divider for forming a plurality of first control signals having frequencies differentiated from each other by a multiplier 1/2k, wherein k is an integer; e. a selecting circuit responsive to the content of said integral part register for selecting one of said control signals from said frequency divider; f. a detecting circuit connected to said selecting circuit and said register means for detecting the content of the fractional part register and producing a second control signal when a predetermined relationship obtains between the number of pulses of the first control signal and the content of the fractional part register; and g. shutter control means responsive to the second control signal from said detecting circuit for controlling the period of actuation of the shutter.
 9. An electric shutter control device comprising:a. register means for storing a shutter speed in the form of a digital signal, the register means including an integral part register which stores an integral part of shutter speed information and a fractional part register which stores a fractional part of the shutter speed information; b. a frequency divider for forming a plurality of first control signal having frequencies differentiated from each other by a multiplier 1/2k, wherein k is an integer;c. a selecting circuit responsive to the content of said integral part register for selecting one of said control signals from said frequency divider; d. a detecting circuit connected to said selecting circuit and said register means for detecting the content of the fractional part register and producing a second control signal when there obtains a predetermined relationship between the number of pulses of the first control signal and the content of the fractional part register; and e. shutter control means responsive to the second control signal from said detecting circuit for controlling the period of actuation of the shutter. 